陽明交通大學 電控工程研究所

 

Ø      VLSI technology

[16] R.Shirota, Y.Itoh, R.Nakayama, M.Momodomi, S.Inoue, R.Kirisawa, Y.Iwata, M.Chiba, and F.Masuoka, “A new NAND cell for ultra high density 5V only EEPROMs,” in Symp. VLSI Technology Dig. Tech. Papers, pp.33-34, June 1988.

[17] R.Kirisawa, S.Aritome, R.Nakayama, T.Endoh, R.Shirota, and F.Masuoka, "A NAND Structured Cell with a New Programming Technology for High Reliable 5 V-Only Flash EEPROM," in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1990.

[18] H.Watanabe, S.Aritome, G.J.Hemink, T.Maruyama, R.Shirota, “Sacling of tunnel oxide thickness for Flash EEPROMs Realizing Stress-Induced Leakage Current Reduction”, in Symp. VLSI Technology Dig. Tech. Papers, pp.47-45, June, 1994.

[19] H.G.Hemink, T.Tanaka, T.Endoh, S.Aritome, and R.Shirota, “Fast and accurate programming method for multilevel NAND flash EEPROM’s,” in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1995.

[20] S.Satoh, K.Shimizu, T.Tanaka, F.Arai, S.Aritome, and R.Shirota, “A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4Gbit NAND Flash memories,” in Symp. VLSI Technologies Dig. Tech. Papers, pp.108-109, June 1998.

[21] M.Ichige, Y.Takeuchi, K.Sugimae, A.Sato, M.Matsui, T.Kamigaki, H.Kutsukake, Y.Ishibashi, M.Saito, S.Mori, H.Meguro, S.Miyazaki, T.Miwa, S.Takahashi, T.Iguchi, N.Kawai, S.Tamon, N.Arai, H.Kamata, T.Minami, H.Iizuka, M.Higashitani, T.Pham, G.Hemink, M.Momodomi and R.Shirota, “A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND Flash EEPROMs,” in Symp. VLSI technologies Dig. Tech. Papers, pp.89-90, June 2003.

 

Ø      VLSI Circuits

[22] T.Tanaka, M.Momodomi, Y.Iwata, Y.Tanaka, H.Oodaira, Y.Itoh, R.Shirota, K.Ohuchi, and F.Masuoka, “A 4-Mbit NAND-EEPROM with tight programmed Vt distribution,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.105-106, June 1990.

[23] T.Tanaka, Y.Tanaka, H.Nakamura, H.Oodaira, S.Aritome, R.Shirota, and F.Masuoka, “A Quick Intelligent Page-Programming Architecture 3V-Only NAND- EEPROMs,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.20-21, June 1992.

[24] T.Tanzawa, T.Tanaka, K.Takeuchi, R.Shirota, S.Aritome, H.Watanabe, G.Hemink, K.Shimizu, S.Sato, Y.Takeuchi, and K.Ohuchi, “A compact on-chip ECC for low cost Flash memories,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.59-60, June 1996.

 

Ø      Other Conferences

[25] M.Momodomi, Y.Iwata, T.Tanaka, Y.Ithoh, R.Shirota, F.Masuoka, “A high density NAND EEPROM with Block-page Programming for Micorcomputer Applications”, in IEEE CICC, pp.10.1.1-4, May, 1989.

 

[26] S.Aritome, R.Kirisawa, T.Endoh, N.Nakayama, R.Shirota, K.Sakui, K.Ohuchi, and F.Masuoka, “Extended Data Retention Characteristics after more than 104 Write and Erase Cycles in EEPROM’s,” in IEEE IRPS 1990, pp.259-264, 1990.

[27] S.Aritome, K.Hatakeyama, T.Endoh, T.Yamaguchi, S.Shuto, H.Iizuka, T.Maruyama, H.Watanabe, G.J.Hemink, T.Tanaka, M.Momodomi, K.Sakui, and R.Shirota, “A 1.13mm² memory cell technology for reliable 3.3V 64M NAND EEPROMs,” in Extended Abstracts of SSDM, pp.446-448, Aug.1993.

[28] M.Momodomi, R.Shirota, K.Sakui, T.Endoh, and F.Masuoka, “Trend of NAND Flash memory and future development,” in International Workshop on Advanced LSI’s, pp.219-225, July 1995.

[29] K.Sakui, T.Tanaka, H.Nakamura, M.Momodomi, T.Endoh, R.Shirota, S.Watanabe, K.Ohuchi, and F.Masuoka, “A shielded bitline sensing technology for a high-density and low-voltage NAND EEPROM design,” in International Workshop on Advanced LSI’s, pp.226-232, July 1995.

[30] K.Sakui, Y.Itoh, R.Shirota, Y.Iwata, S.Aritome, T.Tanaka, K.Imamiya, J.Kishida, M.Momodomi, and J.Miyamoto, “Invited Paper: NAND Flash memory technology and future direction,” in IEEE 1997 NVSMW, pp.1-34, Feb. 1997.

[31] F.Arai, T.Maruyama and R.Shirota, “Extended Data Retention Process Tcdhnology for Highly Reliable Flash EEPROMs of 10⁶ to 10⁷ W/E Cycles”, in IEEE IRPS 1998, pp.378-382, April 1998.

[32] R.Shirota, “Invited paper: A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend.” in Non-Volatile Semiconductor Memory Workshop, pp.22-32, Feb.2000.

[33] R.Shirota, “Test and repair of non-volatile commodity and embedded memories (NAND flash memory) “ in IEEE test Conference, pp.1221,Oct. 2002

[34] R.Shirota, “Invited paper:Future Trends in NAND-Type Flash Memory,” in Extended Abstracts of SSDM, pp.250-251, Aug.2004.

[35] R.Shirota, “Review of NAND Flash reliability,” in IEEE IRPS Tutorial notes, No.223, April 2005.

[36] R.Shirota, “NAND Flash Scaling and Technology Development” in Japan Semiconductor Technology Forum”, Jan. 2006.

[37] R.Shirota, “ Roadmap of the Flash Memory”, IEEE International Workshop on Digital Object Identifier in Memory Technology, Design, and Testing, MTDT, pp: xii – xii, Jun. 2006

[38] BREAKTHROUGH---Memory of the Future, The JAPAN, Journal, August, 2006

[39] R.Shirota, “Scaling trend of Flash memory for File storage”, in Memory, Tech, Design, Testing Workshop, pp.16, 2007.

[40] R.Shirota, “Review of recent development of high density Flash memory”, in New Non-Volatile Memory Workshop at ITRI, session B1, Nov. 2008.

[41] Hsin-Heng Wang, Chiu-Tsung Huang, Shin-Hsien Chen, Kuo, R, Sophia Liu, Ling-Kuey Yang, Houng-Chi Wei, Pittikoun, S., R.Shirota, Chin-chen Cho, ”A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory”, in VLSI-TSA International Symposium, pp.87 – 88, 2008.

[42] R.Shirota, “Review of Recent Flash Memory Development”, in Symposium on Nano Device Technology, Session 1.2, Apr. 2010.

[43] C.H.Liu, Y.M.Lin, R.Shirota, H.C.Wei, L.T.Kuo, C.Han.Liu, S.H.Chen, H.P.Wang, Y.Sakamoto, S.Pittikoun, “Self-Aligned Trench Isolation Recess Effect on Cell Performance and Reliability of 42nm NAND Flash Memory”, in VLSI-TSA, Session 3.1, Apr. 2010.

Ø      IEDM

[1]  F.Masuoka, M.Momodomi, Y.Iwata, and R.Shirora, “New Ultra High Density EPROM and Flash EEPROM with NAND Structured Cell,” in IEDM Tech. Dig., pp.552-555, Dec. 1987.

[2]  M.Momodomi, R.Kirisawa, R.Nakayama, S.Aritome, T.Endoh, Y.Itoh, Y.Iwata, H.Oodaira, T.Tanaka, M.Chiba, R.Shirota, and F.Masuoka, “New device technologies for 5V-only 4Mb EE-PROM with NAND structure cell,” in IEDM Tech. Dig., pp.412-415, Dec. 1988.

[3]  R.Shirota, T.Endo, M.Momodomi, R.Nakayama, S.Inoue, R.Kirisawa, and F.Masuoka, “An accurate model of subbreakdown due to Band-to-Band tunneling and its application,” in IEDM Tech. Dig., pp.26-29, Dec. 1988.

[4]  T.Endo, R.Shirota, Y.Tanaka, R.Nakayama, R.Kirisawa, S.Aritome, and F.Masuoka, “New design technology for EEPROM memory cells with 10 million write/erase cycling endurance,” in IEDM Tech. Dig., pp.599-602, Dec. 1989.

[5]  R.Shirota, R.Nakayama, R.Kirisawa, M.Momodomi, K.Sakui, Y.Itoh, S.Aritome, T.Endoh, F.Hatori, and F.Masuoka, "A 2.3 m2 Memory Cell Structure for 16 Mb NAND EEPROM’s," in IEDM Tech. Dig., pp. 103-106, Dec. 1990.

[6]  S.Aritome, R.Shirota, R.Kirisawa, T.Endoh, R.Nakayama, K.Sakui, and F.Masuoka, “A reliable bi-polarity write/erase technology in Flash EEPROMs,” in IEDM Tech. Dig., pp.111-114, Dec. 1990.

[7]  R.Shirota, T.Yamaguchi, “A New Analytical Model for low Voltage Hot Electron Taking Auger Recombination as well as phonon Scattering Process into Account,” in IEDM Tech. Dig. pp.123-126. 1991.

[8]  S.Aritome, S.Satoh, T.Maruyama, H.Watanabe, S.Shuto, G.J.Hemink, R.Shirota, S.Watanabe, and F.Masuoka, "A 0.67m2 Self-Aligned Shallow Trench Isolation Cell (SA-STI-Cell) for 3V-only 256Mbit NAND EEPROM’s," in IEDM Tech. Dig., pp. 61-64, Dec. 1994.

[9]  S.Aritome, Y.Takeuchi, S.Sato, H.Watanabe, K.Shimizu, G.J.Hemink, and R.Shirota, “A novel side-wall transfer-transistor cell (SWATT cell) for multi-level NAND EEPROM’s,” in IEDM Tech. Dig., pp.275-278, Dec. 1995.

[10] S.Satoh, H.Hagiwara, T.Tanzawa, K.Takeuchi, and R.Shirota, "A Novel Isolation-Scaling Technology for NAND EEPROMs with the Minimized Program Disturbance," in IEDM Tech. Dig., pp. 291-294, Dec. 1997.

[11] A.Goda, W.Moriyama, H.Hazama, H.Iizuka, K.Shimizu, S.Aritome and R.Shirota, “A Novel Surface-Oxidized Barrier-SiN Cell Technology to improve Endurance and Read-Disturb Characteristics for Gigabit NAND Flash Memories.” In IEDM Tech. Dig., pp.771-774, Dec. 2000.

[12] F.Arai, S.Satoh, T.Yaegashi, E.Kamiya, Y.Matunaga, Y.Takeuchi, H.Kamata, A.Shimizu, N.Ohtani, N.Kai, S.Takahashi, W.Moriyama, K.Kugimiya, S.Miyazaki, T.Hirose, H.Meguro, K.Hatakeyama, K.Shimizu, R.Shiorta, “High Density(4.4F²) NAND Flash technology Using Super-Shallow Channel Profile(SSCP) engineering.” In IEDM tech. Dig., pp775-778, Dec. 2000. 

 

Ø      ISSCC

[13] Y.Itoh, M.Momodomi, R.Shirota, Y.Iwata, R.Nakayama, R.Kirisawa, T.Tanaka, K.Toita, S.Inoue, and F.Masuoka, “An Experimental 4Mb CMOS EEPROM with a NAND Structured Cell,” in ISSCC Dig. Tech. Papers, pp.134-135, Feb. 1989.

[14] K.Imamiya, Y.Sugiura, H.Nakamura, T.Himeno, K.Takeuchi, T.Ikehashi, K.Kanda, K.Hosono, R.Shirota, S.Aritome, K.Shimizu, K.Hatakeyama, and K.Sakui, “A 130mm2 256Mb NAND Flash with Shallow Trench Isolation Technology,” in ISSCC Dig. Tech. Papers, pp.112-113, Feb. 1999.

[15] H.Nakamura, K.Imamiya, T.Himeno, T.Yamamura, T.Ikehashi, K.Takeuchi, M. Kanda, K.Hosono, T.Futatsuyama, K.Kawai, R.Shirota, N.Arai, F.Arai, K.Hatakeyama, H.Hazama, M.Saito, H.Meguro, K.Conley, K.Quader, Chen.Jian , “A 125mm² 1Gb NAND flash memory with 10MB/s program throughput “ in ISSCC, Dig. Tech. Parers, pp.82-411, Feb. 2002

 

Ø      VLSI technology

[16] R.Shirota, Y.Itoh, R.Nakayama, M.Momodomi, S.Inoue, R.Kirisawa, Y.Iwata, M.Chiba, and F.Masuoka, “A new NAND cell for ultra high density 5V only EEPROMs,” in Symp. VLSI Technology Dig. Tech. Papers, pp.33-34, June 1988.

[17] R.Kirisawa, S.Aritome, R.Nakayama, T.Endoh, R.Shirota, and F.Masuoka, "A NAND Structured Cell with a New Programming Technology for High Reliable 5 V-Only Flash EEPROM," in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1990.

[18] H.Watanabe, S.Aritome, G.J.Hemink, T.Maruyama, R.Shirota, “Sacling of tunnel oxide thickness for Flash EEPROMs Realizing Stress-Induced Leakage Current Reduction”, in Symp. VLSI Technology Dig. Tech. Papers, pp.47-45, June, 1994.

[19] H.G.Hemink, T.Tanaka, T.Endoh, S.Aritome, and R.Shirota, “Fast and accurate programming method for multilevel NAND flash EEPROM’s,” in Symp. VLSI Technology Dig. Tech. Papers, pp.129-130, June 1995.

[20] S.Satoh, K.Shimizu, T.Tanaka, F.Arai, S.Aritome, and R.Shirota, “A novel Channel Boost Capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4Gbit NAND Flash memories,” in Symp. VLSI Technologies Dig. Tech. Papers, pp.108-109, June 1998.

[21] M.Ichige, Y.Takeuchi, K.Sugimae, A.Sato, M.Matsui, T.Kamigaki, H.Kutsukake, Y.Ishibashi, M.Saito, S.Mori, H.Meguro, S.Miyazaki, T.Miwa, S.Takahashi, T.Iguchi, N.Kawai, S.Tamon, N.Arai, H.Kamata, T.Minami, H.Iizuka, M.Higashitani, T.Pham, G.Hemink, M.Momodomi and R.Shirota, “A novel self-aligned shallow trench isolation cell for 90nm 4Gbit NAND Flash EEPROMs,” in Symp. VLSI technologies Dig. Tech. Papers, pp.89-90, June 2003.

 

Ø      VLSI Circuits

[22] T.Tanaka, M.Momodomi, Y.Iwata, Y.Tanaka, H.Oodaira, Y.Itoh, R.Shirota, K.Ohuchi, and F.Masuoka, “A 4-Mbit NAND-EEPROM with tight programmed Vt distribution,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.105-106, June 1990.

[23] T.Tanaka, Y.Tanaka, H.Nakamura, H.Oodaira, S.Aritome, R.Shirota, and F.Masuoka, “A Quick Intelligent Page-Programming Architecture 3V-Only NAND- EEPROMs,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.20-21, June 1992.

[24] T.Tanzawa, T.Tanaka, K.Takeuchi, R.Shirota, S.Aritome, H.Watanabe, G.Hemink, K.Shimizu, S.Sato, Y.Takeuchi, and K.Ohuchi, “A compact on-chip ECC for low cost Flash memories,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.59-60, June 1996.

 

Ø      Other Conferences

[25] M.Momodomi, Y.Iwata, T.Tanaka, Y.Ithoh, R.Shirota, F.Masuoka, “A high density NAND EEPROM with Block-page Programming for Micorcomputer Applications”, in IEEE CICC, pp.10.1.1-4, May, 1989.

 

[26] S.Aritome, R.Kirisawa, T.Endoh, N.Nakayama, R.Shirota, K.Sakui, K.Ohuchi, and F.Masuoka, “Extended Data Retention Characteristics after more than 104 Write and Erase Cycles in EEPROM’s,” in IEEE IRPS 1990, pp.259-264, 1990.

[27] S.Aritome, K.Hatakeyama, T.Endoh, T.Yamaguchi, S.Shuto, H.Iizuka, T.Maruyama, H.Watanabe, G.J.Hemink, T.Tanaka, M.Momodomi, K.Sakui, and R.Shirota, “A 1.13mm² memory cell technology for reliable 3.3V 64M NAND EEPROMs,” in Extended Abstracts of SSDM, pp.446-448, Aug.1993.

[28] M.Momodomi, R.Shirota, K.Sakui, T.Endoh, and F.Masuoka, “Trend of NAND Flash memory and future development,” in International Workshop on Advanced LSI’s, pp.219-225, July 1995.

[29] K.Sakui, T.Tanaka, H.Nakamura, M.Momodomi, T.Endoh, R.Shirota, S.Watanabe, K.Ohuchi, and F.Masuoka, “A shielded bitline sensing technology for a high-density and low-voltage NAND EEPROM design,” in International Workshop on Advanced LSI’s, pp.226-232, July 1995.

[30] K.Sakui, Y.Itoh, R.Shirota, Y.Iwata, S.Aritome, T.Tanaka, K.Imamiya, J.Kishida, M.Momodomi, and J.Miyamoto, “Invited Paper: NAND Flash memory technology and future direction,” in IEEE 1997 NVSMW, pp.1-34, Feb. 1997.

[31] F.Arai, T.Maruyama and R.Shirota, “Extended Data Retention Process Tcdhnology for Highly Reliable Flash EEPROMs of 10⁶ to 10⁷ W/E Cycles”, in IEEE IRPS 1998, pp.378-382, April 1998.

[32] R.Shirota, “Invited paper: A Review of 256Mbit NAND Flash Memories and NAND Flash Future Trend.” in Non-Volatile Semiconductor Memory Workshop, pp.22-32, Feb.2000.

[33] R.Shirota, “Test and repair of non-volatile commodity and embedded memories (NAND flash memory) “ in IEEE test Conference, pp.1221,Oct. 2002

[34] R.Shirota, “Invited paper:Future Trends in NAND-Type Flash Memory,” in Extended Abstracts of SSDM, pp.250-251, Aug.2004.

[35] R.Shirota, “Review of NAND Flash reliability,” in IEEE IRPS Tutorial notes, No.223, April 2005.

[36] R.Shirota, “NAND Flash Scaling and Technology Development” in Japan Semiconductor Technology Forum”, Jan. 2006.

[37] R.Shirota, “ Roadmap of the Flash Memory”, IEEE International Workshop on Digital Object Identifier in Memory Technology, Design, and Testing, MTDT, pp: xii – xii, Jun. 2006

[38] BREAKTHROUGH---Memory of the Future, The JAPAN, Journal, August, 2006

[39] R.Shirota, “Scaling trend of Flash memory for File storage”, in Memory, Tech, Design, Testing Workshop, pp.16, 2007.

[40] R.Shirota, “Review of recent development of high density Flash memory”, in New Non-Volatile Memory Workshop at ITRI, session B1, Nov. 2008.

[41] Hsin-Heng Wang, Chiu-Tsung Huang, Shin-Hsien Chen, Kuo, R, Sophia Liu, Ling-Kuey Yang, Houng-Chi Wei, Pittikoun, S., R.Shirota, Chin-chen Cho, ”A Study of Slow Erasing Speed at Edge Cell in Nano-Scale NAND Flash Memory”, in VLSI-TSA International Symposium, pp.87 – 88, 2008.

[42] R.Shirota, “Review of Recent Flash Memory Development”, in Symposium on Nano Device Technology, Session 1.2, Apr. 2010.

[43] C.H.Liu, Y.M.Lin, R.Shirota, H.C.Wei, L.T.Kuo, C.Han.Liu, S.H.Chen, H.P.Wang, Y.Sakamoto, S.Pittikoun, “Self-Aligned Trench Isolation Recess Effect on Cell Performance and Reliability of 42nm NAND Flash Memory”, in VLSI-TSA, Session 3.1, Apr. 2010.

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US Pat. 6927998 - Filed Aug 30, 2004

73, Fabrication method of a nonvolatile semiconductor memory
US Pat. 7141474 - Filed Dec 10, 2004

 

Ø      Registered Japanese patent list

1. 特許4271223 半導体集積回路装置

2. 特許4284300 半導体記憶装置

3. 特許4105188 不揮発性半導体記憶装置およびそのデータ消去方法

4. 特許4331053 半導体記憶装置

5. 特許4153856 不揮発性半導体記憶装置

6. 特許4005000半導体記憶装置及びデータ書き込み方法

7. 特許3762385 不揮発性半導体記憶装置

8. 特許3927156 不揮発性半導体記憶装置

9. 特許3762416 不揮発性半導体記憶装置

10. 特許3914142 不揮発性半導体記憶装置及びその製造方法

11. 特許3857640 半導体記憶装置

12. 特許3883534 不揮発性半導体記憶装置、キャッシュメモリシステム、半導体記憶装置、および半導体記憶システム

13. 特許3906190 フラッシュメモリシステムおよびエラー訂正方法

14. 特許4068519 有効期限付き機能利用装置

15. 特許3906177 不揮発性半導体記憶装置

16. 特許4004809 半導体装置及びその動作方法

17. 特許3749891 不揮発性メモリおよび記憶システム

18. 特許4034594 不揮発性半導体メモリ

19. 特許4266089 半導体記憶装置及びその製造方法

20. 特許4109845 不揮発性半導体記憶装置の製造方法

21. 特許4309078 半導体装置及びその製造方法

22. 特許3957985 不揮発性半導体記憶装置

23. 特許3600562 半導体記憶装置

24. 特許4128737 半導体装置及び半導体記憶装置の製造方法

25. 特許4008651 半導体装置とその製造方法

26. 特許3600561 誤り訂正検出回路と半導体記憶装置

27. 特許4064611 半導体装置及びその製造方法

28. 特許4131900 半導体記憶装置及びその製造方法

29. 特許4313941 半導体記憶装置

30. 特許3727864 不揮発性半導体記憶装置

31. 特許3474857 メモリセルのメモリ状態変更方法、不揮発性半導体メモリ装置およびフラッシュメモリシステム

32. 特許3495337 キャッシュメモリシステム、半導体記憶装置、不揮発性半導体記憶装置、半導体記憶システムおよびメモリベリファイ回路

33. 特許3474856 不揮発性半導体記憶装置

34. 特許4031167 不揮発性半導体記憶装置

35. 特許3878374 不揮発性半導体記憶装置

36. 特許4047500 半導体装置及びその製造方法

37. 特許4246831 半導体集積回路装置

38. 特許3540633 半導体装置の製造方法

39. 特許3725708 半導体装置

40. 特許3786513 不揮発性半導体記憶装置

41. 特許4330670 不揮発性半導体記憶装置

42. 特許3557078 不揮発性半導体記憶装置

43. 特許3382151 不揮発性半導体記憶装置

44. 特許3576686 不揮発性半導体記憶装置

45. 特許3207354 不揮発性半導体記憶装置

46. 特許3176019 不揮発性半導体記憶部を含む記憶システム

47. 特許3272903 誤り訂正検出回路と半導体記憶装置

48. 特許3383429 不揮発性半導体記憶装置およびデータ書き込み方法

49. 特許3383427 不揮発性半導体装置

50. 特許3181478 不揮発性半導体記憶装置

51. 特許3405567 不揮発性半導体記憶装置

52. 特許3207592 不揮発性半導体記憶装置

53. 特許3152756 不揮発性半導体記憶装置

54. 特許2647321 不揮発性半導体記憶装置及びこれを用いた記憶システム

55. 特許3170038 不揮発性半導体記憶装置

56. 特許3501405 不揮発性半導体装置の製造方法

57. 特許3162472 不揮発性半導体記憶装置

58. 特許3228996 不揮発性半導体記憶装置

59. 特許3226589 不揮発性半導体記憶装置およびその製造方法

60. 特許3152720 不揮発性半導体記憶装置

61. 特許3210373 不揮発性半導体記憶装置

62. 特許3210355 不揮発性半導体記憶装置

63. 特許3029297 半導体記憶装置

64. 特許3004043 不揮発性半導体メモリ装置

65. 特許3104978 不揮発性半導体記憶装置の制御方法

66. 特許3099887 不揮発性半導体記憶装置

67. 特許2809802 不揮発性半導体記憶装置

68. 特許2818202 不揮発性半導体記憶装置

69. 特許2944104 不揮発性半導体記憶装置

70. 特許2885413 不揮発性半導体メモリ装置

71. 特許2885412 不揮発性半導体メモリ装置

72. 特許2904498 不揮発性半導体メモリ装置およびその製造方法

73. 特許2804066 不揮発性半導体メモリ装置

74. 特許2772020 ＭＯＳ型半導体装置

75. 特許2695881 ＭＯＳ型半導体装置

76. 特許2957586 不揮発性メモリセルの製造方法

77. 特許2718716 不揮発性半導体メモリ装置およびそのデータ書替え方法

78. 特許2732601 不揮発性半導体メモリ装置

79. 特許2667444 不揮発性半導体記憶装置

80. 特許2818190 不揮発性半導体記憶装置およびその製造方法

81. 特許2726432 不揮発性半導体メモリ装置

82. 特許2723247 不揮発性半導体メモリ装置

83. 特許2724150 不揮発性半導体メモリ装置

84. 特許2685770 不揮発性半導体記憶装置

85. 特許2635638 不揮発性半導体メモリ装置の製造方法

86. 特許2573271 不揮発性半導体メモリ装置

87. 特許2618946 不揮発性半導体メモリ装置の製造方法

88. 特許2637127 不揮発性半導体メモリ装置

89. 特許2635630 不揮発性半導体メモリ装置

90. 特許2786629 不揮発性半導体メモリ装置

91. 特許2647101 不揮発性半導体メモリ装置

92. 特許2677565 不揮発性半導体メモリ装置及びその制御方法

93. 特許1863951 半導体装置の製造プロセスにおけるチャージアップ量測定方法

94. 特許2618898 記憶装置

95. 特許2760983 不揮発性半導体記憶装置及びその製造方法