Su, Chau-Chin
Job title Professor
Name Su, Chau-Chin
Email
Office Tel No. 03-5712121 ext31310
website http://msc.cn.nctu.edu.tw/
研究專長 Mixed Analog Digital Circuit Design, High Speed I/O Circuit Design, Mixed Analog Digital Circuit Testing, Clock and Data Recovery Circuit Design, Signal Integrity in High Speed I/O Systems, ATE System Related Testing Issue
Teaching field Introduction to Analog Integrated Circuits
Year Paper Title
2014 Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, and Chen-Yi Lee, “A 48.6-to-105.2μW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications,” IEEE Journal of Solid-State Circuits. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 4, APRIL 2014

, Jun. 2014" href="/en/research/Journal_Papers/Shu-Yu-Hsu-Yingchieh-Ho-Po-Yao-Chang-Chauchin-Su-and-Chen-Yi-Lee-“A-48-6-to-105-2μW-Machine-Learning-Assisted-Cardiac-Sensor-SoC-for-Mobile-Healthcare-Applications-”-IEEE-Journal-of-Solid-State-Circuits-IEEE-JOURNAL-OF-SOLID-STATE-CIRCUITS-VOL-49-NO-4-APRIL-2014 -56565421" target="_blank">Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Chauchin Su, and Chen-Yi Lee, “A 48.6-to-105.2μW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications,” IEEE Journal of Solid-State Circuits. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 4, APRIL 2014

, Jun. 2014
2013 Hung-kai Chen, Yingchieh Ho, and Chauchin Su, “Cumulative Differential Nonlinearity Testing of ADCs,” IEICE Trans. Fund. Electronics, Communications and Computer Sciences, vol.E-95A, no.10, pp. 1768-1775, Oct. 2012., Nov. 2013" href="/en/research/Journal_Papers/Hung-kai-Chen-Yingchieh-Ho-and-Chauchin-Su-“Cumulative-Differential-Nonlinearity-Testing-of-ADCs-”-IEICE-Trans-Fund-Electronics-Communications-and-Computer-Sciences-vol-E-95A-no-10-pp-1768-1775-Oct-2012-66651359" target="_blank">Hung-kai Chen, Yingchieh Ho, and Chauchin Su, “Cumulative Differential Nonlinearity Testing of ADCs,” IEICE Trans. Fund. Electronics, Communications and Computer Sciences, vol.E-95A, no.10, pp. 1768-1775, Oct. 2012., Nov. 2013
2013 Yingchieh Ho, Hung-kai Chen, Chiachi Chang and Chauchin Su, “Energy-effective Sub-threshold Interconnect Design Using High-Boosting Pre-drivers,” IEEE J. on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, pp. 307~313, June 2012., Nov. 2013" href="/en/research/Journal_Papers/Yingchieh-Ho-Hung-kai-Chen-Chiachi-Chang-and-Chauchin-Su-“Energy-effective-Sub-threshold-Interconnect-Design-Using-High-Boosting-Pre-drivers-”-IEEE-J-on-Emerging-and-Selected-Topics-in-Circuits-and-Systems-vol-2-no-2-pp-307-313-June-2012-2210022" target="_blank">Yingchieh Ho, Hung-kai Chen, Chiachi Chang and Chauchin Su, “Energy-effective Sub-threshold Interconnect Design Using High-Boosting Pre-drivers,” IEEE J. on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, pp. 307~313, June 2012., Nov. 2013
2013 Yingchieh Ho, Yu-Sheng Yang, ChiaChi Chang, and Chauchin Su, “A Near-Threshold 480 MHz 78 μW All-Digital PLL with a Bootstrapped DCO,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 11, NOVEMBER 2013

, Nov. 2013" href="/en/research/Journal_Papers/Yingchieh-Ho-Yu-Sheng-Yang-ChiaChi-Chang-and-Chauchin-Su-“A-Near-Threshold-480-MHz-78-μW-All-Digital-PLL-with-a-Bootstrapped-DCO-”-IEEE-JOURNAL-OF-SOLID-STATE-CIRCUITS-VOL-48-NO-11-NOVEMBER-2013 -69480401" target="_blank">Yingchieh Ho, Yu-Sheng Yang, ChiaChi Chang, and Chauchin Su, “A Near-Threshold 480 MHz 78 μW All-Digital PLL with a Bootstrapped DCO,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 11, NOVEMBER 2013

, Nov. 2013
2013 Kao, S. ;  Su, C. "A 0.09W Low Power Front-End Biopotential Amplifier for Biosignal Recording", Volume: PP  Page(s):Date of Publication :   21 Mar 2012
, Jun. 2013" href="/en/research/Journal_Papers/ Tseng-Y-Ho-Y- -Kao-S- -Su-C-A-0-09W-Low-Power-Front-End-Biopotential-Amplifier-for-Biosignal-Recording- Volume-PP- Page-s-1 Date-of-Publication- -21 Mar-2012-13968118" target="_blank"> Tseng, Y. ;Ho, Y. ;  Kao, S. ;  Su, C. "A 0.09W Low Power Front-End Biopotential Amplifier for Biosignal Recording", Volume: PP  Page(s):Date of Publication :   21 Mar 2012
, Jun. 2013
2012 Chauchin Su "Design of a Sub-threshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage Current Reduction Technique", Volume: 59, Page(s): 55 - 59 Date of Publication: Jan. 2012
, Oct. 2012" href="/en/research/Journal_Papers/ Yingchieh-Ho -Chiachi-Chang- -Chauchin-Su-Design-of-a-Sub-threshold-Supply-Bootstrapped-CMOS-Inverter-Based-on-an-Active-Leakage-Current-Reduction-Technique- Volume-59- Page-s-55-59 Date-of-Publication-Jan-2012 -72227460" target="_blank"> Yingchieh Ho ;Chiachi Chang ;  Chauchin Su "Design of a Sub-threshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage Current Reduction Technique", Volume: 59, Page(s): 55 - 59 Date of Publication: Jan. 2012
, Oct. 2012
2012 A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters", Volume: 47   Issue: 5   Pages: 1242-1251   DOI: 10.1109/JSSC.2012.2186722   Published: MAY 2012, Oct. 2012" href="/en/research/Journal_Papers/Ho-Yingchieh-Su-Chauchin-A-0-1-0-3-V-40-123-fJ-bit-ch-On-Chip-Data-Link-With-ISI-Suppressed-Bootstrapped-Repeaters- Volume-47-  Issue-5-  Pages-1242-1251-  DOI-10-1109-JSSC-2012-2186722-  Published-MAY-2012-56640314" target="_blank">Ho, Yingchieh; Su, Chauchin "A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters", Volume: 47   Issue: 5   Pages: 1242-1251   DOI: 10.1109/JSSC.2012.2186722   Published: MAY 2012, Oct. 2012
2011 S.J. Jou C.C. Su, ``The Overview of Computer-Aided Design of Analog Circuits,"
Electronic Monthly, Feb. 1996, pp.67-76., Jul. 2011
2011 C.C. Su, “The Overview of Analog Integrated Circuit Testing,” Electronic Monthly, Nov.
1996, pp.66-71., Jul. 2011
2011 W. H. Hsieh, S. J. Jou and C. C. Su, “Parallel event-driven MOS timing simulator on
distributed memory multiprocessor,” IEE Proceedings Circuits, Devices and Systems,
Vol.143, No.4, August 1996, pp.207-212 (SCI), Jul. 2011
2011 S. J. Jou, J. H. Pan, W. H. Hsieh, C. C. Su, “Current and power waveforms simulators for
CMOS circuits,” Journal of the Chinese Institute of Electrical Engineering, May 1997,
pp.141-148., Jul. 2011
2011 S. J. Jou and I-Yao Chung, “Low-power self-timed circuit design technique,” Electronics
Letters,Vol.33 No.2, January 1997, pp.110-111. (SCI), Jul. 2011
2011 S. J. Jou, C. Y. Chen, E. C. Yang and C. C. Su, “A pipelined Multiplier-Accumulator using
a high-speed, low power static and dynamic full adder design,” IEEE Journal of Solid-State
Circuits, Vol. 32, No. 1, January 1997,pp.114-118. (SCI), Jul. 2011
2011 S. J. Jou, K. F. Liu and C. C. Su, "Circuits design optimization using symbolic approach,"
Journal of the Chinese Institute of Electrical Engineering, Feb. 1997, pp.51-60., Jul. 2011
2011 S. J. Jou, M. F. Perng and C. C. Su, “Hierarchical techniques for symbolic analysis of
electrionic circuits,” IEE Proceedings Circuits, Devices and Systems, Vol. 144, No. 3, June
1997, pp.167-177. (SCI), Jul. 2011
2011 C.C. Su, H.C. Lin, and S.J. Jou, “Design and Testing of a Mixed Signal Matched Filter for
IS-95 CDMA Code Acquisition,” Proc. National Science Council, ROC, Vol. 22, No. 1,
1998, pp.95-102., Jul. 2011
2011 Y.J. Chang, C.L. Lee, J.E. Chen, and C.C. Su, "A Behavior Level Fault Model for the
Closed-loop Operational Amplifier," Journal of Information Science and Engineering. (EI), Jul. 2011
2011 C.C. Su and S.J. Jou, "Decentralized BIST for 1149.1 and 1149.5 Based Interconnects,"
Journal of Electronic Testing - Theory and Applications, (JETTA), Vol. 15, No. 3, Dec.
1999, pp. 255-266. (SCI), Jul. 2011
2011

J.W. Lin, C.L. Lee, C.C. Su, and J.E. Chen, "Fault Diagnosis for Linear Analog Circuits,"
Journal of Electronic Testing - Theory and Applications, (JETTA), Vol 17, 2001.
pp.483-491. (SCI)

, Jul. 2011
2011 C.C. Su and W.L Tzeng, "Configuration Free SoC Interconnect BIST Methodology,"
Journal of Chinese Institute of Electrical Engineering. (EI), Jul. 2011
2011 C.C. Su, Y.T. Chen, "Impulse Response Fault Model and Fault Extraction for Functional
Level Analog Circuit Diagnosis," Journal of Information Science and Engineering. (EI), Jul. 2011
2011 C.C. Su and Y.T. Chen, "Intrinsic Response Extraction for the Analog Test Bus Parasitic
Effect Removal," IEEE Trans. On CAD, IEEE Trans. On Computer-Aided Design of
Integrated Circuits, Vol. 19, No. 4, April 2000, pp.437-445 (full paper). (SCI), Jul. 2011
2011 C.C. Su, Y.T. Chen, and S.J. Jou, "Intrinsic Response for Analog Module Testing Using
Analog Testability Bus," ACM Transcations on Design Automation of Electronic Systems ,
Vol. 6, No.2, April 2001, pp.226-243 (full paper). (SCI), Jul. 2011
2011 C.W. Lu, C.L. Lee, C.C. Su and J.E. Chen, “Analysis of Application of IDDQ Technique to
the Deep Submicron VLSI Testing,” Journal of Electronic Testing Technology and
Applications (JETTA), 18, pp.89-97, 2002. (SCI), Jul. 2011
2011 W.C. Tsai, C.M. Huang, J.J. Wang, J.Y. Jou, and C.C. Su, “Design a Chip Within Half a
Day, iCEER 2005, 08-07, pp. 1-5., Jul. 2011
2011 Wenliang Tseng, Chien-Nan Liu and Chauchin Su, “Passive Reduced-order Macromodeling
for Linear Time-delay Interconnect system,” IEICE Trans. On Electronics, vol. E89-C, no.11,
Nov.2006. (SCI), Jul. 2011
2011 S.M. Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, and Jwu E Chen, “IEEE Standard
1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” IEEE Transaction
on CAD, Nov. 2006, pp.2513-2525. (SCI), Jul. 2011
2011 K.S-M. Li, C.L. Lee, C.C. Su, J.E. Chen, “IEEE Standard 1500 Compatible Oscillation Ring
Test Methodology for Interconnect Delay and Crosstalk Detection,”, Journal of Electronic
Testing: Theory and Applications, August 2007, pp.341-355., Jul. 2011
2011

S.M. Li, Y.W. Chang, C.L. Lee, C.C. Su, and J.E. Chen, “Multilevel Full-Chip Routing
With Testability and Yield Enhancement,” IEEE Trans. On Computer-Aided Design of
Integrated Circuits and Systems, Vol. 26, Issue. 9, Sept. 2007, pp. 1625-1636.

, Jul. 2011
2011 Jen-Chien Hsu and Chauchin Su, “BIST for Measuring Clock Jitter of Charge-Pump
Phase-Locked Loops,” IEEE Transactions on Instrumentation and Measurement, Volume
57, Issue 2, pp. 276–285, 2008., Jul. 2011
2011 Hungwen Lu, Chauchin Su, and Chien-Nan Jimmy Liu, “A Scalable Digitalized Buffer for
Gigabit I/O,” IEEE Transactions on CAS II, vol.55, issue.10, pp.1026-1030, October
2008., Jul. 2011
2011 K.S-M. Li, C.L. Lee, C.C. Su, J.E. Chen, “A Unified Detection Scheme for Crosstalk
Effects in Interconnection Bus,” IEEE Trans. on Very Large Scale Integration Systems,
Vol.17, Iss.2, pp.306-311., Jul. 2011
2011

Hungwen Lu, Chauchin Su, and Chien-Nan Jimmy Liu, “A Tree-Topology Multiplexer
for Multiphase Clocks System,” IEEE Transactions on CAS I, vol.56, issue.1, pp.124-131,
January 2009.

, Jul. 2011
2011 Hungwen Lu, Hsinwen Wang, Chauchin Su, and Chien-Nan Jimmy Liu, “Design of an
All-Digital LVDS Driver,” IEEE Transactions on CAS I, vol.56, issue.8, pp.1635-1644,
August 2009., Jul. 2011
2011 Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu, “Analysis and Design of Wide-Band
Digital Transmission in an Electrostatic-Coupling Intra- Body Communication System”
IEICE Trans. Comm, Vol. E92-B, No. 11,pp.3557-3563 Nov. 2009., Jul. 2011
2011 Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu, “Measuring and Evaluating the
Bioelectrical Impedance of the Human Body Using Deconvolution of a Square
Waveform” IEICE Trans. Information and Systems, Vol.E93-D, No.6, pp.-, Jun. 2010., Jul. 2011
2011 Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu, “Measuring the Transmission
Characteristic of the Human Body in an Electrostatic-Coupling Intra
Body Communication System using a Square Test Stimulus” IEICE Trans. Fundamentals
of Electronics, Communications and Computer Sciences, Vol. E93-A, No.3, pp.664-668,
Mar. 2010., Jul. 2011
2011 Jenchien Hsu and Chauchin Su, “Timing Jitter and Modulation Profile Extraction for
Spread-Spectrum Clocks,” IEEE Transactions on Instrumentation and Measurement,
Volume 59, Issue 4, pp. 847-856, 2010., Jul. 2011
2011 Ying-Chieh Ho, Ya-Ting Chen and Chauchin Su, ” A Power Efficient On-chip Bus
Design with Dynamic Voltage and Frequency Scaling Scheme,” International Journal of
Electrical Engineering, Vol. 17, No. 3, pp207-215, 2010., Jul. 2011
Year Paper Title
2013 Tsunhsin Wang, Yingchieh Ho, Yuhwai Tseng, and Chauchin Su, “A Hearing-Aid Front-End Circuit Based on Low Power And Low Area Mix Mode AGC” The 8th IASTED International Conference on Biomedical Engineering Biomed 2011, Feb.16-18, 2011, Innsbruck, Austria.

, Nov. 2013" href="/en/research/Conference_Papers/Tsunhsin-Wang-Yingchieh-Ho-Yuhwai-Tseng-and-Chauchin-Su-“A-Hearing-Aid-Front-End-Circuit-Based-on-Low-Power-And-Low-Area-Mix-Mode-AGC”-The-8th-IASTED-International-Conference-on-Biomedical-Engineering-Biomed-2011-Feb-16-18-2011-Innsbruck-Austria- -40082995" target="_blank">Tsunhsin Wang, Yingchieh Ho, Yuhwai Tseng, and Chauchin Su, “A Hearing-Aid Front-End Circuit Based on Low Power And Low Area Mix Mode AGC” The 8th IASTED International Conference on Biomedical Engineering Biomed 2011, Feb.16-18, 2011, Innsbruck, Austria.

, Nov. 2013
2013 Yingchieh Ho, Yu-Sheng Yang and Chauchin Su, “A 0.2-0.6 V Ring Oscillator Design Using Bootstrap Technique,” in IEEE Asian Solid-State Circuits Conference (ASSCC) Digest of Tech. Papers, Jeju, Nov. 14th-16th, 2011, pp. 333-336.

, Nov. 2013" href="/en/research/Conference_Papers/Yingchieh-Ho-Yu-Sheng-Yang-and-Chauchin-Su-“A-0-2-0-6-V-Ring-Oscillator-Design-Using-Bootstrap-Technique-”-in-IEEE-Asian-Solid-State-Circuits-Conference-ASSCC-Digest-of-Tech-Papers-Jeju-Nov-14th-16th-2011-pp-333-336- -82354918" target="_blank">Yingchieh Ho, Yu-Sheng Yang and Chauchin Su, “A 0.2-0.6 V Ring Oscillator Design Using Bootstrap Technique,” in IEEE Asian Solid-State Circuits Conference (ASSCC) Digest of Tech. Papers, Jeju, Nov. 14th-16th, 2011, pp. 333-336.

, Nov. 2013
2013 Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Shiou-Ming Chuang, Tze-Zheng Yang, Chauchin Su, and Chen-Yi Lee,” A Sub-100uW Multi-Functional Cardiac Signal Processor for Mobile Healthcare Application,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2012, pp. 156-157, Nov. 2013" href="/en/research/Conference_Papers/Shu-Yu-Hsu-Yingchieh-Ho-Yuhwai-Tseng-Ting-You-Lin-Po-Yao-Chang-Jen-Wei-Lee-Ju-Hung-Hsiao-Shiou-Ming-Chuang-Tze-Zheng-Yang-Chauchin-Su-and-Chen-Yi-Lee-”-A-Sub-100uW-Multi-Functional-Cardiac-Signal-Processor-for-Mobile-Healthcare-Application-”-in-IEEE-Symp-VLSI-Circuits-Digest-of-Tech-Papers-Jun-2012-pp-156-157-32761931" target="_blank">Shu-Yu Hsu, Yingchieh Ho, Yuhwai Tseng, Ting-You Lin, Po-Yao Chang, Jen-Wei Lee, Ju-Hung Hsiao, Shiou-Ming Chuang, Tze-Zheng Yang, Chauchin Su, and Chen-Yi Lee,” A Sub-100uW Multi-Functional Cardiac Signal Processor for Mobile Healthcare Application,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2012, pp. 156-157, Nov. 2013
2013 Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Pei-Yu Hsu, Chien-Ying Yu, Yuhwai Tseng, Tze-Zheng Yang, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee,” A 48.6-to-105.2μW Machine-Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Monitoring,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2013, Nov. 2013" href="/en/research/Conference_Papers/ Shu-Yu-Hsu-Yingchieh-Ho-Po-Yao-Chang-Pei-Yu-Hsu-Chien-Ying-Yu-Yuhwai-Tseng-Tze-Zheng-Yang-Ten-Fang-Yang-Ray-Jade-Chen-Chauchin-Su-Chen-Yi-Lee-”-A-48-6-to-105-2μW-Machine-Learning-Assisted-Cardiac-Sensor-SoC-for-Mobile-Healthcare-Monitoring-”-in-IEEE-Symp-VLSI-Circuits-Digest-of-Tech-Papers-Jun-2013-21282755" target="_blank"> Shu-Yu Hsu, Yingchieh Ho, Po-Yao Chang, Pei-Yu Hsu, Chien-Ying Yu, Yuhwai Tseng, Tze-Zheng Yang, Ten-Fang Yang, Ray-Jade Chen, Chauchin Su, Chen-Yi Lee,” A 48.6-to-105.2μW Machine-Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Monitoring,” in IEEE Symp. VLSI Circuits Digest of Tech. Papers, Jun. 2013, Nov. 2013
2011 Jou, H.F. Liu, and C.C. Su, ``Integrated Circuits Design Optimization Using Symoblic
, Jul. 2011
2011 Hsieh, S.J. Jou, and C.C. Su, ``PMOTA - A Parallel Event-Driven MOS Timing Simulator
, Jul. 2011
2011 Jou, C.Y. Chen, C.C. Su, and C.K. Wang, ``Implementation of High Performance
, Jul. 2011
2011 Lin, C.C. Su, C.K. Wang, and S.J. Jou, ``MixCAD - A Behavioral Level Mixed Mode
, Jul. 2011
2011 Jou, C.Y. Chen, and C.C. Su, ``Implementation of High Performance
, Jul. 2011
2011 Shieh, S.J. Jou, and C.C. Su, ``Network Hopping Technique for Simulation Tools," Proc.
, Jul. 2011
2011 S.T. Yin, C.C. Su, M.T. Shieu, C.K. Wang, and W.I. Way, ``A New VSB Modulation
, Jul. 2011
2011 C.C. Su, Y.R. Cheng, Y.T. Chen, and S. Tenchen, ``Analog Signal Metrology by on-chip
, Jul. 2011
2011 S.J. Kuo, C.L. Lee, J.E. Chen, and C.C. Su, “A Fault Diagnosis Technique for Delta-Sigma
, Jul. 2011
2011 S.J. Kuo, C.L. Lee, J.E. Chen, and C.C. Su, “A Fault Diagnosis Technique for Delta-Sigma
, Jul. 2011
2011 J.S. Liu, Y.H. Jaeng, and C.C. Su, “Code Tracking Loop for the Synchronization of IS-95
, Jul. 2011
2011 Y.T. Chen and C.C. Su, “Parasitic Effect Removal for Analog Measurement in MNABST-1
, Jul. 2011
2011 Y.C. Huang, C.L, Lee, J.E. Chen, and C.C. Su, “Hierarchical Fault Model,” Proc. 10th VLSI
, Jul. 2011
2011 C.C. Su, G.N Chen, and Y.T. Chen, "A Design for Diagnosis Technique for the Delay and
, Jul. 2011
2011 C.C. Su, C.H. Lin, and C.L. Hu, "A Sigma-Delta Modulation Based Carrier Recovery
, Jul. 2011
2011 W.L Tseng, S.F. Yeh, P.J, Huang, and C.C. Su, "Literal Reflection Effect Equivalent
, Jul. 2011
2011 W.L Tseng, S.F, Yeh, P. H. Huang, and C. C. Su, "Qualitative Analysis of N-Coupled
, Jul. 2011
2011 H.W. Lune and C.C. Su, "A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type
, Jul. 2011
2011

H.W. Wang, H.W. Lu and C.C. Su, “A Digitized LVDS Driver with Simultaneous
, Jul. 2011

2011 H.W. Lu and C.C. Su, “A 2.5Gbps Digitalize LVDS Transceiver design,” 15th VLSI Design
, Jul. 2011
2011 H.W. Lu, KuanYu Chen, Chau-Chin Su, “A Digitalize LVDS Driver with Output Level
, Jul. 2011
2011 H.W. Lu, KuanYu Chen, Chau-Chin Su, “A Low Power Tree-Type Multiplexer with
, Jul. 2011
2011 H.W. Lu and C.C. Su, "A Scalable Digitalized Buffer for Gigabit I/O," 19th VLSI Design
, Jul. 2011
2011

JenChien Hsu and Chauchin Su,“BIST for Measuring Signal Eye Opening in High Speed
, Jul. 2011

2011 S.-T. Kao, H.W. Lu, S.M. Chuang and C.C. Su, " A 1.5-V Programmable Front-End
, Jul. 2011
2011 S.-T. Kao, H.W. Lu, S.M. Chuang and C.C. Su, " A Low Power Analog Front-End for
, Jul. 2011
2011 H.W. Lu, J.M. Shih and C.C. Su, " All-Digital Resonant DCO with Inverter-based Tunable
, Jul. 2011
2011 H.W. Lu, C.C. Yang, J.M. Shih and C.C. Su, " A 10Gb/s/pin Transceiver for On-Chip Bus
, Jul. 2011
2011 Ya-Ting Chen, Ying-Chieh Ho and Chauchin Su, ” A Power Efficient On-chip Bus Design
, Jul. 2011
2011 Chou-Ming Kuo, Ying-Chieh Ho and Chauchin Su, ” A 4-bit 5-GSample/s Low-Power
, Jul. 2011
2011 S.J. Jou, M.F. Perng, C.C. Su, and C.K. Wang, ``Hierarchical Techniques for Symbolic
, Jul. 2011
2011 S.J. Jou, K.F. Liu, and C.C. Su, ``Circuit Design Optimization Using Symbolic Approach,"
, Jul. 2011
2011 W.H. Shieh, S.J. Jou, and C.C. Su, ``A Parallel Even-Driven MOS Timing Simulator for
, Jul. 2011
2011 S.J. Jou, C.Y. Chen, E.C. Yang, and C.C. Su, ``A Pipelining Multiplier Accumulator Using
, Jul. 2011
2011 C.C. Su}, et. al., ``A BIST Methodology for Iterative Logic Arrays," Proc. IEEE Int'l Symp.
, Jul. 2011
2011
60. C.C. Su and J.H. Wang, ``A Synthesis Tool for ECC Circuits," Proc. IEEE Int'l Symp. on
Circuits and Systems, Chicago IL USA, May 1993, pp.1706-1709., Jul. 2011
2011 C.Y. Chang and C.C. Su, ``An Universal BIST Methodology for Interconnects," Proc. IEEE
, Jul. 2011
2011 C.C. Su, and K.C. Hwang, ``A Serial Scan Test Vector Compression Mthodology," Proc.
, Jul. 2011
2011 C.C. Su, ``Random Testing Methodologyof Interconnects in a Boundary Scan Environment,"
, Jul. 2011
2011 C.C. Su, K.C. Hwang, and S.J. Jou, ``An IDDQ Based Built-in Concurrent Test Technique
, Jul. 2011
2011 Shyh-Jye Jou; Kou-Fong Liu; Chauchin Su; "Circuits design optimization using symbolic
, Jul. 2011
2011 C.C. Su, S.S. Chiang, S.J. Jou, ``Impulse Response Fault Model and Fault Extraction for
, Jul. 2011
2011 C.C. Su, S.S. Chiang, S.J. Jou, ``Impulse Response Fault Model and Fault Extraction for
, Jul. 2011
2011 S.C. Yin, C.C. Su, et.al., ``A New VSB Modulation Technique and Shaping Filter Design,"
, Jul. 2011
2011 C.C. Su, S.J. Jou, and Y.T. Ting, ``Decentralized BIST for 1149.1 and 1149.5 Based
, Jul. 2011
2011 C.C. Su, Shyh-Shen Hwang, Shyh-Jye Jou, and Yuan-Tzu Ting, ``Syndrome Simulation and
, Jul. 2011
2011 C.C. Su, Yue-Tsang Chen, Shyh-Jye Jou, and Yuan-Tzu Ting, ``Metrology for Analog
, Jul. 2011
2011 , Jul. 2011
2011 C.C. Su, Chenq-Fan Yen, and Jang-Chuang Yo, ``Hardware Efficient Updating Technique
, Jul. 2011
2011 C.C. Su, Hung-Chi Lin, and Shye-Jye Jou, ``Mixed Signal Design of Cascadable Matched
, Jul. 2011
2011 C.C. Su, Y.R. Cheng, Y.T. Chen, and S. T, ``Analog Signal Metrology for Mixed Signal
, Jul. 2011
2011 C.C. Su, Y.T. Chen, and S.J. Jou, ``Parasitic Effect Removal for Analog Measurement in
, Jul. 2011
2011

Chih-Wen Lu; Chung Len Lee; Chen, J.E.; Chauchin Su; "A new IDDQ testing scheme
, Jul. 2011

2011 C.C. Su, “Comprehensive Interconnect BIST Methodology for Virtual Socket Interface,”
, Jul. 2011
2011 Y.T. Chen and C.C. Su, “Analog Module Metrology Using MNABST-1 P1149.4 Test
, Jul. 2011
2011 C.C. Su, S.J. Jeng, and Y.T. Chen, “Boundary Scan BIST Methodology for Reconfigurable
, Jul. 2011
2011 C.C. Su, “A Linear Optimal Test Generation Algorithm for Interconnect Testing,” Proc.
, Jul. 2011
2011

C.C. Su, L.Y. Huang, J.J. Lee, and C.K. Wang, “A Frame-Based Symbol Timing Recovery
, Jul. 2011

2011 C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
, Jul. 2011
2011 C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
, Jul. 2011
2011 C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
, Jul. 2011
2011 C.C. Su, and Y.T. Chen, “Analog Metrology and Stimulus Selection in a Noisy
, Jul. 2011
2011 Y.T. Chen and C.C. Su, “Crosstalk Effect Removal for Analog Measurement in Analog Test
, Jul. 2011
2011 C.C. Su, Y.T. Chen, M.J. Huang, G.N. Chen, and C.L. Lee, “All Digital Built-in Delay and
, Jul. 2011
2011 C.C. Su, et. al., "A Distributed At-Speed TDBI Memory Test System", Proc. 2000 Test
, Jul. 2011
2011 C.W. Lu, C.L. Lee, C.C. Su, and J.E. Chen, "Is IDDQ Testing Not Applicable for Deep
, Jul. 2011
2011 C.W. Lu, C.L. Lee, C.C. Su, and J.E. Chen, "Is IDDQ Testing Not Applicable for Deep
, Jul. 2011
2011 Y.C. Huang, C.L. Lee, J.W. Lin, J.E. Chen and C.C. Su, "A Methodology for Fault Model
, Jul. 2011
2011 J.W. Lin, C.L. Lee, C.C. Su, and J.E. Chen, "Fault Diagnosis for Linear Analog Circuits,"
, Jul. 2011
2011 C.C. Su, et. al., "A Computer Aided Engineering System for Memory BIST," Proc. 2001
, Jul. 2011
2011 C.C. Su, et. al., "A Computer Aided Engineering System for Memory BIST," Proc. 2001
, Jul. 2011
2011 Y.T. Chen and C.C. Su, "Test Waveform Shaping in Mixed Signal Test Bus by
, Jul. 2011
2011 C.C. Su and W.L Tzeng, "Configuration Free SoC Interconnect BIST Methodology," Proc.
, Jul. 2011
2011 Wenliang Tseng; Pojen Huang; Sonfu Yeh; Chauchin Su; "Equivalent circuits for the
, Jul. 2011
2011 Wenliang Tseng; Sonfu Yeh; Pojen Huang; Chauchin Su; "Qualitative analysis of coupled
, Jul. 2011
2011 Chauchin Su; Wei-Juo Wang; Chih-Hu Wang; Tseng Is; "A novel LCD driver testing
, Jul. 2011
2011 Chauchin Su; Chih-Hu Wang; Wei-Juo Wang; Tseng, I.S.; "1149.4 based on-line quiescent
, Jul. 2011
2011 Chauchin Su; Chih-Hu Wang; Wei-Juo Wang; Tseng, I.S.; "1149.4 based on-line quiescent
, Jul. 2011
2011 H.K. Chen and C.C. Su,“A Deconvolution Based RF Test Methodology,”2004 IEEE
, Jul. 2011
2011 K. SM. Li, C.L. Lee, C.C. Su, and J.E. Chen, “A Unified Approach to Detecting Crosstalk
, Jul. 2011
2011 C.C. Su, C.S. Chang, H.W. Huang, D.S. Tu, C.L. Lee, and J. CH. Lin,“Dynamic Analog
, Jul. 2011
2011 H.W. Wang, H.W. Lu, and C.C. Su, “A Digitized LVDS Driver with Simultaneous
, Jul. 2011
2011

H.W. Lu and C.C. Su, “A 5Gbps CMOS LVDS Transmitter with Multi-Phase Tree-Type
, Jul. 2011

2011 S.M.Li, C.L. Lee, Y.W. Chang, C.C. Su, J.E. Chen, “Multi-Level Routing With Testability
, Jul. 2011
2011 S.M. Li, C.L. Lee, T.Q. Jiang, C.C. Su, J.E. Chen, “Finite State Machine Synthesis for
, Jul. 2011
2011

K. S.M. Li, C.L. Lee, C.C. Su, J.E. Chen, “Oscillation Ring Based Interconnect Test Scheme
, Jul. 2011

2011 JenChien Hsu and Chauchin Su, “BIST for Clock Jitter Measurement of Charge-Pump
, Jul. 2011
2011 Wei-Ta Chen, Jen-Chien Hsu, Hong-Wen Lune, Chauchin Su “A Spread Spectrum Clock
, Jul. 2011
2011 Hung Wen Lu, Yin Tin Chang, ChauChin Su, "All digital 625Mbps & 2.5Gbps deskew
, Jul. 2011
2011 Hung Wen Lu, ChauChin Su, ” A 1.25 to 5Gbps LVDS Transmitter with a Novel
, Jul. 2011
2011

Hsin Wen Wang, Hung Wen Lu, ChauChin Su, ”A Self-Calibrate All-Digital 3Gbps SATA
, Jul. 2011

2011 S.M. Li, Y.W. Chang, C.C. Su, C.L. Lee, J.E. Chen, “IEEE Std. 1500 Compatible
, Jul. 2011
2011 JenChien Hsu and Chauchin Su, “BIST for Jitter Measurement and Jitter Decomposition of
, Jul. 2011
2011 Maohsuan Chou, JenChien Hsu and Chauchin Su, “A Digital BIST Methodology for Spread
, Jul. 2011
2011 ChauChin Su, Po-Chen Lin, and HungWen Lu, “ An Inverter Based 2-MHz 42-uW delta
, Jul. 2011
2011 H.K. Chen and Chauchin Su, “A test and diagnosis methodology for RF transceiver,” IEEE
, Jul. 2011
2011 Jenchien Hsu; Maohsuan Chou; Chauchin Su, “Built-in jitter measurement methodology
, Jul. 2011
2011 Hungwen Lu, Chauchin Su, and Chien-Nan Liu, ”A Scalable Digitalized Buffer for
, Jul. 2011
2011 Wei-Chang Liu, Chih-Hsien Lin, Shyh-Jye Jou, Hung-Wen Lu, Chau-Chin Su, Kai-Wei
, Jul. 2011
2011 Shuo-Ting Kao, Hung-Wen Lu, Chau-Chin Su, “A 1.5V 7.5uW Programmable Gain
, Jul. 2011
2011 Hung-Wen Lin, Ying-Chieh Ho, YingLin Fa, and ChauChin Su, "A 5Gb/s Pulse Signaling
, Jul. 2011
Project Category Year Project Title Participator Job Title Period Unit
Research Projects 2013 Su, Chau-Chin 2013.11 ~ 2014.10
Research Projects 2013 Su, Chau-Chin 2013.08 ~ 2014.07
Research Projects 2012 Su, Chau-Chin 2012.08 ~ 2013.07
Research Projects 2012 2012.01 ~ 2013.02
Research Projects 2011 2011.08 ~ 2012.08
Research Projects 2011 2011.08 ~ 2012.07
Research Projects 2011 2011.08 ~ 2011.12
Research Projects 2011 2011.05 ~ 2012.07
Research Projects 2010 2010.08 ~ 2011.07
Research Projects 2010 2010.08 ~ 2011.07
Research Projects 2010 2010.08 ~ 2011.07
Research Projects 2010 2010.05 ~ 2011.04
Research Projects 2009 2009.08 ~ 2011.07
Research Projects 2009 2009.08 ~ 2010.07
Research Projects 2009 2009.08 ~ 2010.07
Research Projects 2009 2009.05 ~ 2010.04
Research Projects 2008 2008.08 ~ 2009.07
Research Projects 2008 2008.08 ~ 2009.07
Research Projects 2008 2008.08 ~ 2009.07
Publish Date Patent Title
2014/06/11  
2014/06/11  
2014/06/11  
2014/06/11  
2013/11/20  
2013/11/20  
2011/07/20
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Lab Title Location
Mixed-Signal Circuit Lab EE 918
Country School Name Department Degree Duration
U. S. A. University of Wisconsin Ph. D. 1983.08 ~ 1989.12
Organization Title Department Job Title Duration
2012.01 ~ 2014.12
2012.01 ~ 2014.12
2011.01 ~ 2013.12
2009.08 ~ 2011.07
2008.08 ~ 2012.07
2004.01 ~ 2007.05
National Chiao Tung University Department of Electrical and Control Engineering Associate Professor 2002.08 ~ 2008.07
2000.08 ~ 2002.07
Honor Category Year
External Honor 2013
External Honor 2012
External Honor 2011
External Honor 2008
External Honor 2008
External Honor 2006
External Honor 2006
External Honor 2006
External Honor 2005
External Honor 2004
External Honor 2004
External Honor 2004
External Honor 2003
External Honor 2002